AMD Ryzen 9 7950X3D is undoubtedly one of the fastest gaming processors. As our recent test showed, this chip outperforms even the Intel Core i9-13900K in places. Much of this is due to the second-generation 3D V-Cache memory, which we didn’t know much about until now. Fortunately, the manufacturer did not keep us in suspense for long and has already provided specific details about the new chiplet present in the new AMD chips. What else have we learned?
AMD has just shared detailed information about the second generation 3D V-Cache memory. The manufacturer also revealed some interesting information about the I / O matrixes in Zen 4 systems.
AMD Ryzen 9 7950X3D vs Intel Core i9-13900K – Performance test of the fastest processors. Who will win the clash of the titans?
The second-generation 3D V-Cache memory was made in 7 nm lithography, i.e. the same one in which the first iteration of 3D V-Cache implemented in the Ryzen 7 5800X3D system was created. The new chiplet, however, is distinguished by a throughput of up to 2.5 TB / s, while the older one was able to reach up to 2 TB / s. The additional cache chip has now been placed on a smaller, smaller, 5-nanometer Zen 4 CCD matrix, which forced some changes in the design. So AMD reduced the 7nm SRAM die, which now covers an area of 36mm2 compared to 41mm2 of the previous generation. However, the total number of transistors remains the same at around 4.7 billion. This is a very high level of density that is not found in other parts of the processor. This is largely due to the 7 nm process, which is specialized for SRAM, as well as the lack of typical control circuits (they are located on the basic matrix).
AMD Ryzen 9 7950X3D has been overclocked to 5.9 GHz. Unusual methods were used
The stacked L3 SRAM chiplet is connected to the base via two types of vertical connection – the Power TSV transfers power between the chiplets, while the Signal TSV transfers data between the units. In the first generation 3D V-Cache design, both TSV types were in the L3 region, however now AMD has extended the TSV from L3 to the L2 zone. It is worth noting that in the 3D stacking AMD again used TSMC SoIC technology, which consists in direct connection of two dies (without the use of solder). While the technology has seen some improvements, the minimum TSV pitch has not changed.
AMD EPYC 9004 – official debut of EPYC Genoa server processors with up to 96 Zen 4 cores
AMD’s presentation also includes many new details about the 6nm I/O dies (IODs) used in the Ryzen 7000 and EPYC Genoa processors. As it turns out, the I / O system in the EPYC Genoa models covers an area of as much as 386.88 m2 and has as many as 11 billion transistors. For comparison, the I/O matrix in Ryzen 7000 takes up only 117.8 mm2 and has 3.37 billion transistors, while the 12-nanometer I/O system in Ryzen 5000 takes up 125 mm2 and has 2.09 billion transistors. As an added curiosity, the Ryzen 7000 processors only have two Global Memory Interconnect 2 (GMI2) links that connect the compute chiplets to the IOD, while the Genoa models use dual-GMI3 (wide mode) links that offer additional benefits in some high-intensity tasks memory bandwidth.
Zen 4 Raphael 6nm client I/O die:
– 128b DDR5 PHY + 32b for ECC (8b per 32b channel)
– 2x GMI3 Ports, 3x CCDs are not possible. :p
– 28x PCIe 5, Zen1/2/3 cIOD had 32x PCIe lanes.
So AMD reduced the waste for the client market.
– Really just one RDNA2 WGP, 128 Shader “Cores” https://t.co/bkqdVvhgrn pic.twitter.com/erYxTw1p8h— Locuza (@Locuza_) March 4, 2023
Source: Tom’s Hardware, @Locuza_